Today, one of the major challenges in the Performance Engineering of real-time systems is the integration of design models and runtime aspects. The timing behavior at runtime has to be matched with the design in order to identify the timing failures in design and deviations from the real-time requirements. Many tools exist for tracing the execution/communication and performing measurements of runtime properties. However, these tools do not allow the integration with system design models – the most suitable level for engineers for performance verification and optimization as well as decision-making.
RATE will allow the architect performing a continuous system performance engineering cycle between design and runtime, thus ensuring the quality of the running real-time system while reducing the design and development efforts and costs, and getting valuable feedback that can be used to boost the productivity and provide lessons-learnt for future generations of the product.
The following objectives will be fulfilled:
- Verify if timing requirements are met in the system execution (CPU) or communication (network/bus) and identify potential timing bottlenecks.
- Help the architect understanding the system timing behaviour based on numerical and graphical statistics for the system execution/communication.
- Perform consistency check between runtime and models to validate timing related assumptions taken at the design phase.
- Help the architect correcting timing errors and exploring design alternatives at the design phase based on the system runtime behaviour before investing time and efforts in implementing and testing.
RATE will integrate the FED4SAE technology Time4Sys. By relying on the Time4Sys design model and the Time4Sys trace model, RATE will automatically benefit from current and future connections to Time4Sys of the various existing model-driven performance engineering tools such as design tools, scheduling analysis and simulation tools as well as tracing tools all at once. This will guarantee high flexibility and add a valuable agnostic character to RATE since it will be possible to easily integrate it in any runtime, design and any scheduling verification environment.
Runtime Architect gives to the architect access to knowledge on the system timing behavior based on the processing of runtime traces, thus allowing him to easily perform correction during validation and before delivery. Runtime Architect will allow reducing the design efforts (~15% gain estimated) while improving development efficiency as well as validation speed (~30% faster timing validation).
Through the integration of the Time4Sys technology, it will be easy to use Runtime Architect in any runtime, design and timing verification environment, thus offering to our customer a seamlessly integrated solution that will deliver a full, round-trip support for runtime traces analysis, design modelling and timing verification. Performance engineers will be able to rapidly integrate runtime aspects collected from traces into their design models. They will be able to start from runtime traces and then change the system configuration virtually to easily predict the performance impact of modified timing properties of tasks, schedulers or hardware. Runtime Architect will enable performance engineers to quickly iterate their designs as many times as they want, for both new developments and evolutionary extension and optimization of existing systems.